The innovative architecture driving the highest utilization and lowest latency
DDR Memory Controller, OMC
TM
Get to know the ORBIT Memory Subsystem IP that consists of an interconnect, memory controller, and PHY IPs that work in unison to create maximum system synergies.
Achieve exceptional connectivity performance and design flexibility using an automated end-to-end interconnect generation flow.
Meet high-speed memory PHY IPs that deliver the lowest power and area, enabling solutions across AI/ML, high-performance computing (HPC), and automotive.
TM
ORBIT Memory Controller, OMC
Delivers excellent performance in addition to high utilization and ultra-low latency, achieved by its proprietary out-of-scheduling algorithm and high-speed implementation. Designed to address the needs of next-generation SoCs, the OMC saves a significant amount of area and power while supporting the highest levels of the DRAM bandwidth.
The OMC integrates seamlessly with the OPENEDGES ORBIT DDR PHY(OPHY) and ORBIT On-Chip Interconnect (OIC) to deliver a complete memory subsystem. The OMC also supports third-party DDR PHYs, providing full functional verification for use with any PHY implementation.
Key Features
DRAM Support
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JEDEC compliant LPDDR5x/5/4x/4/3, DDR4/3, GDDR6, HBM3 support
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Up to 4 ranks/channel (configurable)
High Performance
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A proprietary out-of-order scheduling algorithm
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Dual-PHY control for 2x DRAM channel bandwidth with a single OMC instance
Low Power Consumption
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Ultra-low power consumption with HW-controlled dynamic DRAM frequency scaling
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Automatically handles training activities required for frequency change
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Automated DRAM power management
Special Features
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BFE (Bus Front End) for multi-master ports (optional)
Key Advantages
Intensive DRAM Utilization
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Over 90% DRAM utilization using a proprietary out-of-order scheduling algorithm
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Optimal pipeline architecture
Ultra-Low Power Consumption
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Hardware-controlled dynamic DRAM frequency scaling
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Automates training activities required for frequent changes
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Highly area-efficient
Extremely Low Latency
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Low latency even in high utilization scenarios
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Suppression of peak latency using the latency-aware algorithms
Safety & Security
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Inline ECC
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Security Firewall
DDR Memory Type
OMC Configurable Options
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DRAM types (LPDDR5x/5, DDR4, LPDDR4x/4, DDR3/LPDDR3, GDDR6)
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Channel DQ width (x16, x32, x64)
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Number of AXI master ports (up to 8)
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AXI master data width and frequency
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Request queue depth
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Write and read data queue depth
OMC Deliverables
OMC is packaged with the following items to all eligible companies:
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IP Core RTL
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Standalone Simulation Environment
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Management SW
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IP Documentation