TSS(The Six Semiconductor) is OPENEDGES’ strategic PHY partner and this OPHY is designed by TSS.
The OPHY utilizes state-of-the-art architecture in full custom analog mixed-signal design to overcome the problem of long-term impedance drift and clock phase drift, allowing impedance and clock phase updates without the need to interrupt data traffic. The programmable timing PHY boundary combines flexibility with analog precision, and the result is ultra low PHY read/write latency between OMC and the OPHY DRAM without sacrificing performance.
|DDR Type||Foundry process technology||Available|
|GDDR6 PHY||TSMC 12nm||Now|
|LPDDR54 PHY||Samsung 14nm||Now|
|LPDDR4 PHY||Samsung 14nm||Now|
|LPDDR54 PHY||TSMC 12nm||TBD|
LPDDR54 Key Advantages.
- DRAM supports
. JESD209-5A(LPDDR5), JESD209-4C(LPDDR4), JESD209-4-1(LPDDR4X) compliant
. Operating speed up to 6400Mbps in LPDDR5, 4266Mbps in LPDDR4X
. Multiple DFICLK : CK :WCK ratios
- High Performance
. Channel equalization with FFE, CTLE, and DFE
. Voltage and temperature drift compensation to maintain optimal data eye
- DFT Features
. Internal and external loopback through datapath
. IO bypass mode for internal clock observation.
. Analog test ports for internal analog signals observation
- Special Features
. •Firmware-based PHY independent initialization of DRAM and training