Total memory subsystem IP
for high performance SoC
OPENEDGES is the only SoC IP vendor that provides both NoC and Memory controller IP.
There are two important areas to achieve high performance for your SoC;
(1). On-chip communication (through the NoC) and
(2). Memory access (through the memory controller).
Traditionally you need to get an NoC from an NoC IP vendor and a DRAM controller from a separate DRAM controller IP vendor. In this case, even if the NoC and the DRAM controller provide good performance respectively, you may encounter some performance issues when you use the NoC and the DRAM controller together due to interoperability issue.
OPENEDGES provides both IPs making interoperability a non-issue. In addition to that, OPENEDGES provides ActiveQoS technology to aid in achieving the best performance throughout the system.
The combination of OIC and OMC can provide significant aid in achieving the best performance. OIC and OMC used by themselves also provide feature sets that provide a competitive advantage.. OIC uses two significant technologies; HyperPath and LDA. HyperPath can facilitate data transfer high frequency and high efficiency. LDA can provide floor plan flexibility and physical design friendliness. Through the use of those technologies, OPENEDGES’ customers can achieve 2x data throughput with 1/2 area compared to other conventional solutions. OMC uses its own proprietary out-of-order scheduling algorithm; Cohort scheduling algorithm so users can achieve much higher DRAM utilization while preserving short latency targets.
OPENEDGES’ NoC “OIC” and DDR controller “OMC” work together to provide the best system performance. OPENEDGES’ patented ActiveQoS technology provides the best system performance by having OIC and OMC communicate with each other to exchange QoS information.
OIC internally uses HyperPath technology internally for data transfer. HyperPath technology facilitates high data throughput. Additionally a proprietary HXI (Hyper-path eXpress Interface) protocol is used for the internal communication. HXI is designed to achieve 100% data transfer efficiency and low latency, which are vital for high performance SoCs like AI application.
With traditional NoCs, register slices are used for long distance transfer in an SoC. In the event, that the distance is very long, a significant number of register slices need to be inserted. The end result is that gate count is impacted. A second order affect is that timing closure will be difficult because all of the register slices are in a same clock domain.
OIC uses a different approach, –LDA (Long Distance Asynchronous) protocol. By using the proprietary LDA protocol, customers can attain much significantly smaller gate count and a much easier physical design than the register slice scheme
OIC can use a different approach, which is LDA (Long Distance Asynchronous) protocol. By using the proprietary LDA protocol, you can have much smaller gate count and much easier physical design than the register slice scheme.
Cohort scheduling algorithm
OMC uses its own proprietary out-of-order scheduling algorithm; Cohort scheduling algorithm. The Cohort scheduling algorithm can achieve very high DRAM utilization while preserving low latency compared to other conventional solutions.