Total memory subsystem IP
for high performance SoC
OPENEDGES is only an IP provider who provides both NoC and Memory controller.
There are two important areas to achieve high performance for your SoC;
(1). On-chip communication (through NoC) and
(2). Memory access (through memory controller).
Traditionally you need to get an NoC from an NoC IP vendor and a DRAM controller from another DRAM controller IP vendor. In this case, even if the NoC and the DRAM controller provide good performance respectively, you may encounter some performance issues when you use the NoC and the DRAM controller together due to some interoperability reason.
OPENEDGES provides both IPs so you don’t have to concern about such interoperability issue between them. In addition to that, OPENEDGES provides ActiveQoS technology so you can achieve the best performance throughout the system.
Although the combination of OIC and OMC can achieve the best performance, OIC and OMC themselves have supreme technologies. OIC uses two proprietary technologies; HyperPath and LDA. HyperPath can make data transfer high frequency and high efficiency. LDA can provide floor plan flexibility and physical design friendliness. By using those technologies, you can achieve 2x data throughput with 1/2 area compared to other conventional solutions. OMC uses its own proprietary out-of-order scheduling algorithm; Cohort scheduling algorithm so you can achieve much better DRAM utilization while preserving short latency.
OPENEDGES’ NoC “OIC” and DDR controller “OMC” work together to provide the best system performance. OPENEDGES’ patented ActiveQoS technology provides the best system performance by having OIC and OMC to communicate each other to exchange QoS information.
OIC internally uses HyperPath technology for data transfer. The HyperPath technology can provide high data throughput. And proprietary HXI (Hyper-path eXpress Interface) protocol is used for the internal communication. HXI is designed to achieve 100% data transfer efficiency and short latency, which are vital for high performance SoCs like AI application.
Traditionally register slices are used for long distance transfer in an SoC. In this case, when the distance is very long, a lot of register slices need to be inserted so the gate count becomes big and timing closure will be difficult because all of the register slices are in a same clock domain so the domain size becomes big.
OIC can use a different approach, which is LDA (Long Distance Asynchronous) protocol. By using the proprietary LDA protocol, you can have much smaller gate count and much easier physical design than the register slice scheme.
Cohort scheduling algorithm
OMC uses its own proprietary out-of-order scheduling algorithm; Cohort scheduling algorithm. The Cohort scheduling algorithm can achieve very high DRAM utilization while preserving low latency compared to other conventional solutions.