Seoul, South Korea, May 31st, 2024 --- OPENEDGES Technology, Inc. (OPENEDGES), the leading provider of memory subsystem IPs, is pleased to announce a recent licensing agreement with ASICLAND. This agreement involves implementing OPENEDGES’ comprehensive memory subsystem IPs, including the DDR memory controller (OMC), DDR PHY (OPHY), and NoC interconnect (OIC), for a project of ASICLAND’s customer, using advanced LPDDR5X at the 12nm process node. These IPs will be deployed for the development of a Retrieval Augmented Generation (RAG) system. The RAG system is a cutting-edge natural language processing (NLP) technique that combines the strengths of both document retrieval system and Large Language Models (Generative AI). OPENEDGES’ memory subsystem IPs are designed to deliver exceptional performance with low latency and high DRAM utilization for AI application.
Founded in 2016, ASICLAND is a comprehensive ASIC design house specializing in the development of high-tech semiconductors using process nodes ranging from 5nm to 28nm. ASICLAND offers complete architecture design services and turnkey solutions, delivering fully packaged and tested chips to significantly reduce overall design schedules. The company has been the only Korean member of the TSMC Value Chain Alliance (VCA) since 2019 and an Arm Approved Design Partner (ADP) since 2018.
By integrating OPENEDGES’ advanced memory subsystem IPs, ASICLAND aims to significantly enhance the performance and reliability of their AI application SoCs, minimizing chip size and saving power for their customers. OPENEDGES’ memory subsystem IPs are designed to work synergistically, providing exceptional performance with over 30% better DRAM utilization and approximately 50% reduced PHY area, alongside easier integration and flexible configuration options. Additionally, this combined memory subsystem IP facilitates large feedback control loops within the SoC’s entire memory subsystem, enhancing Quality-of-Service (QoS), performance, bandwidth, and latency. Overall, the proprietary QoS technology effectively manages latency, reducing average and peak latencies by nearly half, resulting in reduced area and lower power consumption. Moreover, the feedback loop-based advanced traffic control enabled by the ActiveQoS feature ensures that the latency-sensitive traffic is prioritized and delivered on time, reducing latency and congestion by managing traffic based on buffer status and urgency.
“OPENEDGES’ IPs are designed to meet dynamic demands and offer a comprehensive solution that provides a holistic view of the entire memory system,” said Sean Lee, CEO of OPENEDGES Technology. “We are pleased to collaborate with ASICLAND once again, combining our advanced technologies to drive innovation in the semiconductor landscape.”
“OPENEDGES is our go-to company for memory subsystem IPs,” said JongMin Lee, CEO of ASICLAND. “Since our initial contact in 2019, they have been a trusted partner. We appreciate their dedicated approach to our projects and their commitment to ensuring the success of our customers’ journey.”
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