OMC is very small and highly configurable DDR memory controller.
It provides very high performance through advanced memory controller design based on a proprietary out-of-order scheduling algorithm and high speed implementation technique.
DDR Memory Type
|DDR Type||Typical Applications||Available|
|HBM2/2E Controller||HPC (AI/ML) / Coin / Data Center||Q4,20|
|HBM3 Controller||HPC (AI/ML) / Coin / Data Center||1H,21|
- Very high DRAM utilization
. +90% DRAM utilization through proprietary out of order scheduling algorithm
. Highly optimized pipeline architecture
- Ultra low power consumption
. HW controlled dynamic DRAM frequency scaling
. Automatically handles training activities required for frequency change
. Very small size
- Ultra low latency
. Ultra low latency even at high utilization
. Peak latency suppression through latency-aware algorithm.
. Exceptionally low write latency
- Safety & Security
. Full ECC
. Security firewall