Together with us,
Architect a new IP industry.

Do you want adventure? Do you want to be an inventor? Do you want more fun?
OPENEDGES is just fit for you and you are just the one we need


RTL design engineer

. Performance architect, RTL engineer, Verification engineer.
. C++, SystemC, System Verilog, UVM methodology
. Experienced or an architect who wants to learn more with us.

DDR PHY digital & analog engineer

.Top architect, Digital RTL engineer, Analog engineer
.System Verilog. P&R guide. High speed I/O
.Experienced or an engineer who has passion for DDR PHY

Application engineer

.IP generation, delivery, troubleshooting, support
.Verilog-HDL,VHDL, System-Verilog
.Experienced in SoC design, IP integration, .

Field Application engineer

.Experienced in SoC design, IP integration, Memory subsystem
.Technical issue communication in English
.Full ownership of all the pre sales technical support

Web EDA frontend developer

. Web based GUI SW engineer
. Javascript, Typescript, ReactJS, ELK. GUI SW developer
. Experienced Developer or Beginner who wants to advance as a professional

IT admin & developer

.Internal server system set up & maintenance
.Network environment: FIrewall, VPN & etc
.Personal mini PC, Server Farm environment