Together with us,
Architect a new IP industry.
Do you want adventure? Do you want to be an inventor? Do you want more fun?
OPENEDGES is just fit for you and you are just the one we need .
RTL design engineer
. Performance architect, RTL engineer, Verification engineer.
. C++, SystemC, System Verilog, UVM methodology
. Experienced or an architect who wants to learn more with us.
DDR PHY digital & analog engineer
.Top architect, Digital RTL engineer, Analog engineer
.System Verilog. P&R guide. High speed I/O
.Experienced or an engineer who has passion for DDR PHY
.IP generation, delivery, troubleshooting, support
.Experienced in SoC design, IP integration, .
Web EDA frontend developer
. Web based GUI SW engineer
. Experienced Developer or Beginner who wants to advance as a professional
IT admin & developer
.Internal server system set up & maintenance
.Network environment: FIrewall, VPN & etc
.Personal mini PC, Server Farm environment