OPENEDGES' Memory Subsystem IP – DDR Controller & NoC interconnect licensed for high end 4K multimedia SoC ( Dec, 18)

Dec, 2018

OPENEDGES, the leading IP provider in the memory subsystem, announced its ORBITTM memory subsystem IP – DDR memory controller & Network on-Chip (NoC) interconnect IP has been licensed again for the leading multimedia SoC company targeting for 4K surveillance & smart networking cameras.

OPENEDGES’ ORBITTM DDR Memory Controller IP (OMCTM) features excellent DRAM bandwidth utilization and ORBITTM Network-on-Chip Interconnect (OICTM) is a highly optimized on chip interconnect fabric for the high end SoC. DDR Memory Controller IP (OMCTM) and Network-on-Chip Interconnect (OICTM) are tightly coupled. This combined memory subsystem IP brings lots of synergy in terms of performance, bandwidth, latency & others.

This smart network camera SoC supports high resolution 4K 60fps encoding, new generation ISP, intelligent vision processing & others. Overall, system behavior is very complicated and performance demanding. So bandwidth efficiency and quality-of-service (QoS) in the memory subsystem are the two most critical factors of the high end SoC design. Initially this customer selected a DDR controller and a Network on-chip (NoC) interconnect from two different IP providers. However, the combination failed to deliver the required DRAM bandwidth and quality-of-service (QoS) and, as a result, overall system performance suffered a lot. Only after both DDR controller (OMCTM) and Network-on-Chip Interconnect (OICTM) from OPENEDGES have been used, it has become possible to meet the demand of their intelligent high end SoC. Some of the killer features offered by the OMC and OIC combination for the customer are as below.

  • DDR Utilization has been increased by 30% than before and this enabled them to achieve target DRAM bandwidth.
  • Average & peak latency of the latency-sensitive master IPs have been decreased to almost half than before with the highly effective quality-of-service management feature (ActiveQoSTM).
  • Timing closing at the SoC backend design time got dramatically easier & faster than before with the LDATM technology.
  • Frequency of the backbone has been almost doubled with the HyperPathTM technology, leading to 1/2x area and, more importantly, lower power consumption.

Nowadays, SoC designers suffer a lot from wide range of issues related to memory subsystem designs including difficulty of high-speed timing closing, lack of DRAM bandwidth, difficulty of quality-of-service (QoS) management, and eventually time-to-market delay. New breakthrough in the memory subsystem IP solution is required to meet these tough challenges.

OPENEDGES’ highly efficient memory subsystem IP solution is a game changer for the new SoC designs. OPENEDGES is the only IP company providing both the DDR controller (OMCTM) and the Network-on-Chip (OICTM). OPENEDGES’ ORBITTM memory subsystem IP has tightly coupled DDR controller and Network on-chip interconnect to bring maximum efficiency based on their synergy. It enables more sophisticated and performance demanding SoC systems with higher bandwidth efficiency and higher power efficiency.

OPENEDGES also provides AI accelerator IP (ENLIGHTTM), which is also tightly integrated with the memory subsystem IP, and it will be officially released very soon.